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preliminary 512kx36/1mx18 pipelined sram with nobl? architecture cy7c1370av25 cy7c1372av25 cypress semiconductor corporation 3901 north first street san jose ca 95134 408-943-2600 july 10, 2000 25 features ? zero bus latency, no dead cycles between write and read cycles fast clock speed: 167, 150, 133, and 100 mhz fast access time: 3.4, 3.8, 4.2, 5.0 ns internally synchronized registered outputs eliminate the need to control oe single 2.5v + 5% single we (read/write) control pin positive clock-edge triggered, address, data, and con- trol signal registers for fully pipelined applications interleaved or linear 4-word burst capability individual byte write (bws a - bws d ) control (may be tied low) cen pin to enable clock and suspend operations three chip enables for simple depth expansion jtag boundary scan available in 119- ball bump bga and 100-pin tqfp packages functional description the cy7c1370av25 and cy7c1372av25 srams are de- signed to eliminate dead cycles when transitions from read to write or vice versa. these srams are optimized for 100 percent bus utilization and achieves zero bus latency. they integrate 524,288x36 and 1,048,576x18 sram cells, respec- tively, with advanced synchronous peripheral circuitry and a 2- bit counter for internal burst operation. the cypress synchro- nous burst sram family employs high-speed, low-power cmos designs using advanced triple-layer polysilicon, dou- ble-layer metal technology. each memory cell consists of four transistors and two high-valued resistors. all synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, depth-expansion chip enables (ce 1 , ce 2 and ce 3 ), cycle start input (adv/ld ), clock enable (cen ), byte write selects (bws a , bws b , bws c and bws d ), and read-write control (we ). bws c and bws d apply to cy7c1370av25 only. address and control signals are applied to the sram during one clock cycle, and two cycles later, its associated data oc- curs, either read or write. a clock enable (cen ) pin allows operation of the cy7c1370av25/cy7c1372av25 to be suspended as long as necessary. all synchronous inputs are ignored when (cen ) is high and the internal device registers will hold their previous values. there are three chip enable (ce 1 , ce 2 , ce 3 ) pins that allow the user to deselect the device when desired. if any one of these three are not active when adv/ld is low, no new mem- ory operation can be initiated and any burst cycle in progress is stopped. however, any pending data transfers (read or write) will be completed. the data bus will be in high impedance state two cycles after chip is deselected or a write cycle is initiated. the cy7c1370av25 and cy7c1372av25 have an on-chip 2- bit burst counter. in the burst mode, the cy7c1370av25 and cy7c1372av25 provide four cycles of data for a single ad- dress presented to the sram. the order of the burst sequence is defined by the mode input pin. the mode pin selects be- tween linear and interleaved burst sequence. the adv/ld sig- nal is used to load a new external address (adv/ld =low) or increment the internal burst counter (adv/ld =high) output enable (oe ) and burst sequence select (mode) are the asynchronous signals. oe can be used to disable the out- puts at any given time. zz may be tied to low if it is not used. four pins are used to implement jtag test capabilities. the jtag circuitry is used to serially shift data to and from the device. jtag inputs use lvttl/lvcmos levels to shift data during this testing mode of operation. no bus latency and nobl are trademarks of cypress semiconductor corporation. zbt is a trademark of integrated device technology. . clk a x cen we bws x ce 1 ce ce 2 oe 256kx36/ memory array logic block diagram dq x data-in reg. q d ce control and write logic 3 adv/ld mode dp x cy7c1370 cy7c1372 a x dq x dp x bws x 512kx18 x = 18:0 x = 19:0 x = a, b, c, d x = a, b x = a, b x = a, b x = a, b, c, d x = a, b, c, d outout registers and logic
cy7c1370av25 cy7c1372av25 preliminary 2 selection guide 7c1370a-167 7c1372a-167 7c1370a-150 7c1372a-150 7c1370a-133 7c1372a-133 7c1370a-100 7c1372a-100 maximum access time (ns) 3.4 3.8 4.2 5.0 maximum operating current (ma) com ? l 350 310 280 250 maximum cmos standby current (ma) 30 30 30 30 shaded areas contain advance information. pin configurations a a a a a 1 a 0 dnu dnu v ss v dd a a a a a a v ddq v ss dqb dqb dqb v ss v ddq dqb dqb v ss v dd v dd dqa dqa v ddq v ss dqa dqa v ss v ddq v ddq v ss dqc dqc v ss v ddq dqc dqc v dd v ss dqd dqd v ddq v ss dqd dqd dqd v ss v ddq a a ce 1 ce 2 bws a ce 3 v dd v ss clk we cen oe a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld nc dnu cy7c1370av25 100-pin tqfp packages a a a a a 1 a 0 dnu dnu v s v dd a a a a a a a nc nc v ddq v ss nc dpa dqa dqa v ss v ddq dqa dqa v ss v dd v dd dqa dqa v ddq v ss dqa dqa nc nc v ss v ddq nc nc nc nc nc nc v ddq v ss nc nc dqb dqb v ss v ddq dqb dqb nc v dd v ss dqb dqb v ddq v ss dqb dqb dpb nc v ss v ddq nc nc nc a a ce 1 ce 2 nc nc bws b bws a ce 3 v dd v ss clk we cen oe a a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld nc mode dnu cy7c1372av25 bws d mode bws c dqc dqc dqc dqc dpc dqd dqd dpd dqd nc dpb dqb dqa dqa dqa dqa dpa dqb dqb (512k x 36) (1m x 18) bws b v dd v dd a dnu dnu
cy7c1370av25 cy7c1372av25 preliminary 3 pin configurations (continued) 234567 1 a b c d e f g h j k l m n p r t u dq a v ddq nc nc dq c dq d dq c dq d aa aa av ddq nc a v ddq v ddq v ddq v ddq nc 64m a dq c dq c dq d dq d tms v dd a nc dp d a a adv/ld ancnc v dd aanc v ss v ss nc dp b dq b dq b dq a dq b dq b dq a dq a dnu tdi tdo v ddq tck v ss v ss v ss v dd(1) v ss v ss v ss v ss mode ce 1 v ss oe v ss v ddq bws c a v ss we v ddq v dd v dd(1) v dd v ss clk nc bws a cen v ss v ddq v ss nc nc a a a1 a0 v ss v dd nc cy7c1370av25 (512k x 36) - 7 x 17 bga dp c dq b a32m dq c dq b dq c dq c dq c dq b dq b dq a dq a dq a dq a dp a dq d dq d dq d dq d bws d 119-ball bump bga bws b 234567 1 a b c d e f g h j k l m n p r t u 32m dq a v ddq nc nc nc dq b dq b dq b dq b aa aa av ddq nc a nc v ddq nc v ddq v ddq v ddq nc nc nc 64m a dq b dq b dq b dq b nc nc nc nc tms v dd a a dp b a a adv/ld ancnc v dd aanc v ss v ss nc nc dp a dq a dq a dq a dq a dq a dq a dq a dnu tdi tdo v ddq tck v ss v ss v ss v dd(1) v ss v ss v ss v ss v ss mode ce 1 v ss nc oe v ss v ddq bws b av ss nc v ss we nc v ddq v dd v dd(1) v dd nc v ss clk nc nc bws a cen v ss nc v ddq v ss nc nc nc a a a a1 a0 v ss nc v dd sn cy7c1372av25 (1m x 18) - 7 x 17 bga
cy7c1370av25 cy7c1372av25 preliminary 4 pin definitions (100-pin tqfp) x18 pin location x36 pin location name i/o type description 37, 36, 32 ? 35, 44 ? 50, 80 ? 84, 99, 100 37, 36, 32 ? 35, 44 ? 50, 81-84, 99, 100 a0 a1 a input- synchronous address inputs used to select one of the 266,144 ad- dress locations. sampled at the rising edge of the clk. 93, 94 93, 94, 95, 96 bws a bws b bws c bws d input- synchronous byte write select inputs, active low. qualified with we to conduct writes to the sram. sampled on the rising edge of clk. bws a controls dq a and dp a , bws b con- trols dq b and dp b , bws c controls dq c and dp c , bws d controls dq d and dp d . 88 88 we input- synchronous write enable input, active low. sampled on the rising edge of clk if cen is active low. this signal must be asserted low to initiate a write sequence. 85 85 adv/ld input- synchronous advance/load input used to advance the on-chip ad- dress counter or load a new address. when high (and cen is asserted low) the internal burst counter is ad- vanced. when low, a new address can be loaded into the device for an access. after being deselected, adv/ld should be driven low in order to load a new address. 89 89 clk input-clock clock input. used to capture all synchronous inputs to the device. clk is qualified with cen . clk is only rec- ognized if cen is active low. 98 98 ce 1 input- synchronous chip enable 1 input, active low. sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/deselect the device. 97 97 ce 2 input- synchronous chip enable 2 input, active high. sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/deselect the device. 92 92 ce 3 input- synchronous chip enable 3 input, active low. sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. 86 86 oe input- asynchronous output enable, active low. combined with the synchro- nous logic block inside the device to control the direction of the i/o pins. when low, the i/o pins are allowed to behave as outputs. when deasserted high, i/o pins are three-stated, and act as input data pins. oe is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected. 87 87 cen input- synchronous clock enable input, active low. when asserted low the clock signal is recognized by the sram. when deas- serted high the clock signal is masked. since deassert- ing cen does not deselect the device, cen can be used to extend the previous cycle when required. (a)58, 59, 62, 63, 68, 69, 72 ? 73 (b)8, 9, 12, 13, 18, 19, 22 ? 23 (a)52, 53, 56 ? 59, 62, 63, (b)68, 69, 72 ? 75, 78, 79 (c)2, 3, 6 ? 9, 12, 13, (d)18, 19, 22 ? 25, 28, 29 dq a dq b dq c dq d i/o- synchronous bidirectional data i/o lines. as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, they deliver the data contained in the memory location specified by a [17:0] during the previous clock rise of the read cycle. the direction of the pins is controlled by oe and the internal control logic. when oe is asserted low, the pins can behave as outputs. when high, dq a ? dq d are placed in a three-state condition. the outputs are automatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of oe .
cy7c1370av25 cy7c1372av25 preliminary 5 74, 24 51, 80, 1, 30 dp a dp b dp c dp d i/o- synchronous bidirectional data parity i/o lines. functionally, these sig- nals are identical to dq [31:0] . during write sequences, dp a is controlled by bws a , dp b is controlled by bws b , dp c is controlled by bws c , and dp d is controlled by bws d . 31 31 mode input strap pin mode input. selects the burst order of the device. tied high selects the interleaved burst order. pulled low selects the linear burst order. mode should not change states during operation. when left floating mode will de- fault high, to an interleaved burst order. 15, 16, 41, 65, 66, 91 15, 16, 41, 65, 66, 91 v dd power supply power supply inputs to the core of the device. 4, 11, 20, 27, 54, 61, 70, 77 4, 11, 20, 27, 54, 61, 70, 77 v ddq i/o power supply power supply for the i/o circuitry. 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 v ss ground ground for the device. should be connected to ground of the system. 14 14 nc - no connects. reserved for address expansion to 512k depths. 38, 39, 42, 43 38, 39, 42, 43 dnu - do not use pins. these pins should be left floating. pin definitions (100-pin tqfp) (continued) x18 pin location x36 pin location name i/o type description pin definitions (119 bga) x18 pin location x36 pin location name i/o type description p4, n4, a2, a3, a4, a5, a6, b3, b5, c2, c3, c5, c6, g4, r2, r6, t2, t3, t5, t6 p4, n4, a2, a3, a4, a5, a6, b3, b5, c2, c3, c5, c6, r2, r6, g4, t3, t4, t5 a0 a1 a input- synchronous address inputs used to select one of the 266,144 address locations. sampled at the rising edge of the clk. l5, g3 l5, g5, g3, l3 bws a bws b bws c bws d input- synchronous byte write select inputs, active low. qualified with we to conduct writes to the sram. sampled on the rising edge of clk. bws a controls dq a and dp a , bws b controls dq b and dp b , bws c controls dq c and dp c , bws d controls dq d and dp d . h4 h4 we input- synchronous write enable input, active low. sampled on the ris- ing edge of clk if cen is active low. this signal must be asserted low to initiate a write sequence. b4 b4 adv/ld input- synchronous advance/load input used to advance the on-chip ad- dress counter or load a new address. when high (and cen is asserted low) the internal burst counter is advanced. when low, a new address can be loaded into the device for an access. after being deselected, adv/ld should be driven low in order to load a new address. k4 k4 clk input-clock clock input. used to capture all synchronous inputs to the device. clk is qualified with cen . clk is only recognized if cen is active low. e4 e4 ce 1 input- synchronous chip enable 1 input, active low. sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/deselect the device.
cy7c1370av25 cy7c1372av25 preliminary 6 f4 f4 oe input- asynchronous output enable, active low. combined with the syn- chronous logic block inside the device to control the direction of the i/o pins. when low, the i/o pins are allowed to behave as outputs. when deasserted high, i/o pins are three-stated, and act as input data pins. oe is masked during the data portion of a write sequence , during the first clock when emerging from a deselected state and when the device has been deselected. m4 m4 cen input- synchronous clock enable input, active low. when asserted low the clock signal is recognized by the sram. when deasserted high the clock signal is masked. since deasserting cen does not deselect the device, cen can be used to extend the previous cycle when required. (a)p7, n6, l6, k7, h6, g7, f6, e7 (b)n1, m2, l1, k2, h1, g2, e2, d1 (a)p7, n7, n6, m6, l7, l6, k7, k6 (b)d7, e7, e6, f6, g7, g6, h7, h6 (c)d1, e1, e2, f2, g1, g2, h1, h2 (d)p1, n1, n2, m2, l1, l2, k1, k2 dq a dq b dq c dq d i/o- synchronous bidirectional data i/o lines. as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, they deliver the data con- tained in the memory location specified by a [17:0] dur- ing the previous clock rise of the read cycle. the di- rection of the pins is controlled by oe and the internal control logic. when oe is asserted low, the pins can behave as outputs. when high, dq a ? dq d are placed in a three-state condition. the outputs are au- tomatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is de- selected, regardless of the state of oe . d6, p2 p6, d6, d2, p2 dp a dp b dp c dp d i/o- synchronous bidirectional data parity i/o lines. functionally, these signals are identical to dq [31:0] . during write se- quences, dp a is controlled by bws a , dp b is con- trolled by bws b , dp c is controlled by bws c , and dp d is controlled by bws d . r3 r3 mode input strap pin mode input. selects the burst order of the device. tied high selects the interleaved burst order. pulled low selects the linear burst order. mode should not change states during operation. when left floating mode will default high, to an interleaved burst order. c4, j2, j4, j6, r4 c4, j2, j4, j6, r4 v dd power supply power supply inputs to the core of the device. a1, a7, f1, f7, j1, j7, m1, m7, u1, u7 a1, a7, f1, f7, j1, j7, m1, m7, u1, u7 v ddq i/o power supply power supply for the i/o circuitry. d3, d5, e3, e5, f3, f5, g5, h3, h5, k3, k5, l3, m3, m5, n3, n5, p3, p5, r5 d3, d5, e3, e5, f3, f5, h3, h5, k3, k5, m3, m5, n3, n5, p3, p5, r5 v ss ground ground for the device. should be connected to ground of the system. j3, j5 j3, j5 v dd(1) input- asynchronous these pins have to be tied to a voltage level > vih. they need not be tied to vdd. u5 u5 tdo jtag serial output synchronous serial data-out to the jtag circuit. delivers data on the negative edge of tck. u3 u3 tdi jtag serial input synchronous serial data-in to the jtag circuit. sampled on the rising edge of tck. pin definitions (119 bga) (continued) x18 pin location x36 pin location name i/o type description
cy7c1370av25 cy7c1372av25 preliminary 7 u2 u2 tms te s t m o d e s e - lect synchronous this pin controls the test access port state machine. sampled on the rising edge of tck. u4 u4 tck jtag-clock clock input to the jtag circuitry. t6, t1 t4, t1 32m, 64m - no connects. reserved for address expansion. b1, b2, b7, c1, c7, d2, d4, d7, e1, e6, f2, g1, g6, h2, h7, k1, k6, l2, l4, l7, m6, n2, n7, p1, p6, r1, r5, r7,t7 b2, b7, c7, d4, l4, l7, r1, r5, r7, t1,t7 nc - no connects. u6 u6 dnu - do not use pins. pin definitions (119 bga) (continued) x18 pin location x36 pin location name i/o type description
cy7c1370av25 cy7c1372av25 preliminary 8 introduction functional overview the cy7c1370av25/cy7c1372av25 are synchronous-pipe- lined burst nobl srams designed specifically to eliminate wait states during write/read transitions. all synchronous in- puts pass through input registers controlled by the rising edge of the clock. the clock signal is qualified with the clock enable input signal (cen ). if cen is high, the clock signal is not recognized and all internal states are maintained. all synchro- nous operations are qualified with cen . all data outputs pass through output registers controlled by the rising edge of the clock. maximum access delay from the clock rise (t co ) is 3.6 ns (166-mhz device). accesses can be initiated by asserting chip enable (ce 1 , ce 2 , ce 3 on the tqfp, ce 1 on the bga) active at the rising edge of the clock. if clock enable (cen ) is active low and adv/ld is asserted low, the address presented to the device will be latched. the access can either be a read or write operation, depending on the status of the write enable (we ). bws [d:a] can be used to conduct byte write operations. write operations are qualified by the write enable (we ). all writes are simplified with on-chip synchronous self-timed write circuitry. synchronous chip enable (ce 1 , ce 2 , ce 3 on tqfp, ce 1 on bga) and an asynchronous output enable (oe ) simplify depth expansion. all operations (reads, writes, and deselects) are pipelined. adv/ld should be driven low once the device has been deselected in order to load a new address for the next operation. single read accesses a read access is initiated when the following conditions are satisfied at clock rise: (1) cen is asserted low, (2) chip en- able asserted active, (3) the write enable input signal we is deasserted high, and (4) adv/ld is asserted low. the ad- dress presented to the address inputs is latched into the ad- dress register and presented to the memory core and control logic. the control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. at the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 3.6 ns (166-mhz device) provided oe is active low. after the first clock of the read access the output buffers are controlled by oe and the internal control logic. oe must be driven low in order for the device to drive out the requested data. during the second clock, a subsequent operation (read/write/deselect) can be initiated. deselecting the device is also pipelined. therefore, when the sram is deselected at clock rise by one of the chip enable signals, its output will three-state following the next clock rise. burst read accesses the cy7c1370av25/cy7c1372av25 have an on-chip burst counter that allows the user the ability to supply a single ad- dress and conduct up to four reads without reasserting the address inputs. adv/ld must be driven low in order to load a new address into the sram, as described in the single read access section above. the sequence of the burst counter is determined by the mode input signal. a low input on mode selects a linear burst mode, a high selects an interleaved burst sequence. both burst counters use a0 and a1 in the burst sequence, and will wrap-around when incremented suf- ficiently. a high input on adv/ld will increment the internal burst counter regardless of the state of chip enables inputs or we . we is latched at the beginning of a burst cycle. therefore, the type of access (read or write) is maintained throughout the burst sequence. single write accesses write access are initiated when the following conditions are satisfied at clock rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, and (3) the write signal we is asserted low. the address presented to a x is loaded into the address register. the write signals are latched into the control logic block. on the subsequent clock rise the data lines are automatically three-stated regardless of the state of the oe input signal. this allows the external logic to present the data on dq and dqp (dq a,b,c,d /dp a,b,c,d for cy7c1370av25 and dq a,b /dp a,b for cy7c1372av25). in addition, the address for the subsequent access (read/write/deselect) is latched into the address register (provided the appropriate control signals are assert- ed). on the next clock rise the data presented to dq and dp (dq a,b,c,d /dp a,b,c,d for cy7c1370av25 & dq a,b /dp a,b for cy7c1372av25) (or a subset for byte write operations, see write cycle description table for details) inputs is latched into the device and the write is complete. the data written during the write operation is controlled by bws (bws a,b,c,d for cy7c1370av25 & bws a,b for cy7c1372av25) signals. the cy7c1370av25 and cy7c1372av25 provides byte write capability that is de- scribed in the write cycle description table. asserting the write enable input (we ) with the selected byte write select (bws ) input will selectively write to only the desired bytes. bytes not selected during a byte write operation will remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. byte write ca- pability has been included in order to greatly simplify read/modify/write sequences, which can be reduced to sim- ple byte write operations. because the cy7c1370av25/cy7c1372av25 is a common i/o device, data should not be driven into the device while the outputs are active. the output enable (oe ) can be deasserted high before presenting data to the dq and dp (dq a,b,c,d /dp a,b,c,d for cy7c1370av25 & dq a,b /dp a,b for cy7c1372av25) inputs. doing so will three-state the output drivers. as a safety precaution, dq and dp (dq a,b,c,d /dp a,b,c,d for cy7c1370av25 & dq a,b /dp a,b for cy7c1372av25) are automatically three-stated during the data portion of a write cycle, regardless of the state of oe . burst write accesses the cy7c1370av25/cy7c1372av25 has an on-chip burst counter that allows the user the ability to supply a single ad- dress and conduct up to four write operations without reas- serting the address inputs. adv/ld must be driven low in order to load the initial address, as described in the single write access section above. when adv/ld is driven high on the subsequent clock rise, the chip enables (ce 1 , ce 2 , and ce 3 ) and we inputs are ignored and the burst counter is in- cremented. the correct bws (bws a,b,c,d for cy7c1370av25 & bws a,b for cy7c1372av25) inputs must be driven in each cycle of the burst write in order to write the correct bytes of data.
cy7c1370av25 cy7c1372av25 preliminary 9 notes: 1. x = ? don't care, ? 1 = logic high, 0 = logic low, ce stands for all chip enables active. bws x = 0 signifies at least one byte write select is active, bws x = valid signifies that the desired byte write selects are asserted, see write cycle description table for details. 2. write is defined by we and bws x . see write cycle description table for details. 3. the dq and dp pins are controlled by the current cycle and the oe signal. 4. cen = 1 inserts wait states. 5. device will power-up deselected and the i/os in a three-state condition, regardless of oe . 6. oe assumed low. cycle description truth table [1, 2, 3, 4, 5, 6] operation address used ce cen adv/ ld/ we bws x clk comments deselected external 1 0 l x x l-h i/os three-state following next recognized clock. suspend - x 1 x x x l-h clock ignored, all operations suspended. begin read external 0 0 0 1 x l-h address latched. begin write external 0 0 0 0 valid l-h address latched, data presented two valid clocks later. burst read operation internal x 0 1 x x l-h burst read operation. previous ac- cess was a read operation. ad- dresses incremented internally in conjunction with the state of mode. burst write operation internal x 0 1 x valid l-h burst write operation. previous ac- cess was a write operation. ad- dresses incremented internally in conjunction with the state of mode. bytes written are deter- mined by bws [d:a] . interleaved burst sequence first address second address third address fourth address a[1:0] a[1:0] a[1:0] a[1:0] 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst sequence first address second address third address fourth address a[1:0] a[1:0] a[1:0] a[1:0] 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10
cy7c1370av25 cy7c1372av25 preliminary 10 write cycle description [1] function (cy7c1370av25) we bws d bws c bws b bws a read 1xxxx write - no bytes written 01111 write byte 0 - (dqa and dpa) 01110 write byte 1 - (dqb and dpb) 01101 write bytes 1, 0 01100 write byte 2 - (dqc and dpc) 01011 write bytes 2, 0 01010 write bytes 2, 1 01001 write bytes 2, 1, 0 01000 write byte 3 - (dqd and dpd) 00111 write bytes 3, 0 00110 write bytes 3, 1 00101 write bytes 3, 1, 0 00100 write bytes 3, 2 00011 write bytes 3, 2, 0 00010 write bytes 3, 2, 1 00001 write all bytes 00000 function (cy7c1372av25) we bws b bws a read 1 x x write - no bytes written 0 1 1 write byte 0 - (dq a and dp a ) 010 write byte 1 - (dq b and dp b ) 001 write both bytes 0 0 0
cy7c1370av25 cy7c1372av25 preliminary 11 ieee 1149.1 serial boundary scan (jtag) the cy7c1370av25/cy7c1372av25 incorporates a serial boundary scan test access port (tap) in the bga package only. the tqfp package does not offer this functionality. this port operates in accordance with ieee standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance. these functions from the ieee specification are excluded because their inclusion places an added delay in the critical speed path of the sram. note that the tap controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant taps. the tap operates using jedec standard 2.5v i/o logic levels. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are inter- nally pulled up and may be unconnected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. test access port (tap) - test clock the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this pin unconnected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information into the regis- ters and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruc- tion that is loaded into the tap instruction register. for infor- mation on loading the instruction register, see the tap control- ler state diagram. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is con- nected to the most significant bit (msb) on any register. test data out (tdo) the tdo output pin is used to serially clock data-out from the registers. the output is active depending upon the current state of the tap state machine (see tap controller state dia- gram). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. ta p r e g is t ers registers are connected between the tdi and tdo pins and allow data to be scanned into and out of the sram test circuit- ry. only one register can be selected at a time through the instruction registers. data is serially loaded into the tdi pin on the rising edge of tck. data is output on the tdo pin on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruc- tion register. this register is loaded when it is placed between the tdi and tdo pins as shown in the tap controller block diagram. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as de- scribed in the previous section. when the tap controller is in the captureir state, the two least significant bits are loaded with a binary ? 01 ? pattern to allow for fault isolation of the board level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and output pins on the sram. several no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the x36 configuration has a 69-bit-long reg- ister, and the x18 configuration has a 69-bit-long register. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instruc- tions can be used to capture the contents of the input and output ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in the identification register defi- nitions table. tap instruction set eight different instructions are possible with the three-bit in- struction register. all combinations are listed in the instruction code table. three of these instructions are listed as re- served and should not be used. the other five instructions are described in detail below. the tap controller used in this sram is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. the tap controller can- not be used to load address, data, or control signals into the sram and cannot preload the input or output buffers. the
cy7c1370av25 cy7c1372av25 preliminary 12 sram does not implement the 1149.1 commands extest or intest or the preload portion of sample / preload; rather it performs a capture of the inputs and output ring when these instructions are executed. instructions are loaded into the tap controller during the shift- ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo pins. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is to be ex- ecuted whenever the instruction register is loaded with all 0s. extest is not implemented in the tap controller, and there- fore this device is not compliant to the 1149.1 standard. the tap controller does recognize an all-0 instruction. when an extest instruction is loaded into the instruction register, the sram responds as if a sample / preload instruction has been loaded. there is one difference between the two instructions. unlike the sample / preload instruction, extest places the sram outputs in a high-z state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo pins and allows the idcode to be shifted out of the device when the tap con- troller enters the shift-dr state. the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr state. it also places all sram outputs into a high-z state. sample / preload sample / preload is a 1149.1 mandatory instruction. the preload portion of this instruction is not implemented, so the tap controller is not fully 1149.1 compliant. when the sample / preload instructions are loaded into the instruction register and the tap controller is in the capture- dr state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. the user must be aware that the tap controller clock can only operate at a frequency up to 10 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output will under- go a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guarantee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register w ill capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller's capture set-up plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample / preload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck# captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the bound- ary scan register between the tdi and tdo pins. note that since the preload part of the command is not implemented, putting the tap into the update to the update- dr state while performing a sample / preload instruction will have the same effect as the pause-dr command. bypass when the bypass instruction is loaded in the instruction reg- ister and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo pins. the advan- tage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instructions are not implemented but are reserved for future use. do not use these instructions.
cy7c1370av25 cy7c1372av25 preliminary 13 tap controller state diagram test-logic reset test-logic/ idle select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select ir-scan capture-dr shift-ir exit1-ir pau s e - i r exit2-ir update-ir 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 note: the 0/1 next to each state represents the value at tms at the rising edge of tck.
cy7c1370av25 cy7c1372av25 preliminary 14 tap controller block diagram 0 0 1 2 . . 29 30 31 boundary scan register identification register 0 1 2 . . . . . 0 1 2 instruction register bypass register selection circuitry selection circuitry ta p c o nt rol le r tdi tdo tck tms tap electrical characteristics over the operating range [7, 8] parameter description test conditions min. max. unit v oh1 output high voltage i oh = ? 2.0 ma 1.7 v v oh2 output high voltage i oh = ? 100 a 2.1 v v ol1 output low voltage i ol = 2.0 ma 0.7 v v ol2 output low voltage i ol = 100 a 0.2 v v ih input high voltage 1.7 v dd + 0.3 v v il input low voltage ? 0.3 0.7 v i x input load current gnd v i v ddq ? 5 5 a notes: 7. all voltage referenced to ground 8. overshoot: v ih (ac)< v dd +1.5v for t< t tcyc /2, undershoot: v il (ac)< 0.5v for t< t tcyc /2, power-up: v ih <2.6v and v dd <2.4v and v ddq <1.4v for t<200 ms.
cy7c1370av25 cy7c1372av25 preliminary 15 tap ac switching characteristics over the operating range [9, 10] parameter description min. max unit t tcyc tck clock cycle time 100 ns t tf tck clock frequency 10 mhz t th tck clock high 40 ns t tl tck clock low 40 ns set-up times t tmss tms set-up to tck clock rise 10 ns t tdis tdi set-up to tck clock rise 10 ns t cs capture set-up to tck rise 10 ns hold times t tmsh tms hold after tck clock rise 10 ns t tdih tdi hold after clock rise 10 ns t ch capture hold after clock rise 10 ns output times t tdov tck clock low to tdo valid 20 ns t tdox tck clock low to tdo invalid 0 ns notes: 9. t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 10. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns.
cy7c1370av25 cy7c1372av25 preliminary 16 tap timing and test conditions (a) tdo c l = 20 pf z 0 = 50 ? gnd 1.25v test clock test mode select tck tms test data-in tdi test data-out tdo t tcyc t tmsh t tl t th t tmss t tdis t tdih t tdox t tdov 50 ? 2.5v 0v all input pulses 1.25v
cy7c1370av25 cy7c1372av25 preliminary 17 identification register definitions instruction field value description cy7c1370av25 cy7c1372av25 revision number (31:29) 000 version number. cypress device id (28:12) tbd tbd defines the type of sram. cypress jedec id (11:1) tbd allows unique identification of sram vendor. id register presence (0) 1 indicate the presence of an id register. scan register sizes register name bit size instruction 3 bypass 1 id 32 boundary scan 70(cy7c1370av25) 51(cy7c1372av25) identification codes instruction code description extest 000 captures the input/output ring contents. places the boundary scan register between the tdi and tdo. forces all sram outputs to high-z state. this instruction is not 1149.1 compliant. idcode 001 loads the id register with the vendor id code and places the register be- tween tdi and tdo. this operation does not affect sram operation. sample z 010 captures the input/output contents. places the boundary scan register be- tween tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruction is reserved for future use. sample/preload 100 captures the input/output ring contents. places the boundary scan register between tdi and tdo. does not affect the sram operation. this instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. reserved 101 do not use: this instruction is reserved for future use. reserved 110 do not use: this instruction is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operation.
cy7c1370av25 cy7c1372av25 preliminary 18 boundary scan order (512k x 36) bit # signal name bump id bit # signal name bump id 1 a 2r 36 ce3 6b 2 a 3t 37 bwsa 5l 3 a 4t 38 bwsb 5g 4 a 5t 39 bwsc 3g 5 a 6r 40 bwsd 3l 6 a 3b 41 ce2 2b 7 a 5b 42 ce1 4e 8 dpa 6p 43 a 3a 9 dqa 7n 44 a 2a 10 dqa 6m 45 dpc 2d 11 dqa 7l 46 dqc 1e 12 dqa 6k 47 dqc 2f 13 dqa 7p 48 dqc 1g 14 dqa 6n 49 dqc 1d 15 dqa 6l 50 dqc 1d 16 dqa 7k 51 dqc 2e 17 nc 7t 52 dqc 2g 18 dqb 6h 53 dqc 1h 19 dqb 7g 54 sn 5r 20 dqb 6f 55 dqd 2k 21 dqb 7e 56 dqd 1l 22 dqb 6d 57 dqd 2m 23 dqb 7h 58 dqd 1n 24 dqb 6g 59 dqd 2p 25 dqb 6e 60 dqd 1k 26 dpb 7d 61 dqd 2l 27 a 6a 62 dqd 2n 28 a 5a 63 dpd 1p 29 a 4g 64 mode 3r 30 a 4a 65 a 2c 31 adv/ld 4b 66 a 3c 32 oe# 4f 67 a 5c 33 cen# 4m 68 a 6c 34 we# 4h 69 a1 4n 35 clk 4k 70 a0 4p boundary scan order (1m x 18) bit # signal name bump id bit # signal name bump id 1 a 2r 36 dqb 2e 2 a 2t 37 dqb 2g 3 a 3t 38 dqb 1h 4 a 5t 39 sn 5r 5 a 6r 40 dqb 2k 6 a 3b 41 dqb 1l 7 a 5b 42 dqb 2m 8 dqa 7p 43 dqb 1n 9 dqa 6n 44 dpb 2p 10 dqa 6l 45 mode 3r 11 dqa 7k 46 a 2c 12 nc 7t 47 a 3c 13 dqa 6h 48 a 5c 14 dqa 7g 49 a 6c 15 dqa 6f 50 a1 4n 16 dqa 7e 51 a0 4p 17 dpa 6d 18 a6t 19 a6a 20 a5a 21 a4g 22 a4a 23 adv/ld 4b 24 oe 4f 25 cen 4m 26 we 4h 27 clk 4k 28 ce3 6b 29 bwsa 5l 30 bwsb 3g 31 ce2 2b 32 ce1 4e 33 a3a 34 a2a 35 dqb 1d
cy7c1370av25 cy7c1372av25 preliminary 19 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ..................................... ? 65 c to +150 c ambient temperature with power applied .................................................. ? 55 c to +125 c supply voltage on v dd relative to gnd .........? 0.5v to +3.6v dc voltage applied to outputs in high z state [12] ....................................? 0.5v to v ddq + 0.5v dc input voltage [12] ................................? 0.5v to v ddq + 0.5v current into outputs (low)......................................... 20 ma static discharge voltage .......................................... >2001v (per mil-std-883, method 3015) latch-up current.................................................... >200 ma operating range range ambient temperature [11] v dd /v ddq com ? l 0 c to +70 c 2.5 5% electrical characteristics over the operating range parameter description test conditions min. max. unit v dd / v ddq power supply voltage 2.375 2.625 v v oh output high voltage v dd = min., i oh = ? 1.0 ma [13] 1.7 v v ol output low voltage v dd = min., i ol = 1.0 ma [13] 0.7 v v ih input high voltage 1.7 v v il input low voltage [12] ? 0.3 0.7 v i x input load current gnd v i v ddq 5 a input current of mode 30 a i oz output leakage current gnd v i v ddq, output disabled 5 a i dd v dd operating supply v dd = max., i out = 0 ma, f = f max = 1/t cyc 6.0-ns cycle, 167 mhz 350 ma 6.7-ns cycle, 150 mhz 310 ma 7.5-ns cycle, 133 mhz 280 ma 10-ns cycle, 100 mhz 250 ma i sb1 automatic ce power-down current ? ttl inputs max. v dd , device deselected, v in > v ih or v in < v il f = f max = 1/t cyc 6.0-ns cycle, 167 mhz 130 ma 6.7-ns cycle, 150 mhz 110 ma 7.5-ns cycle, 133 mhz 95 ma 10-ns cycle, 100 mhz 80 ma i sb2 automatic ce power-down current ? cmos inputs max. v dd , device deselected, v in 0.3v or v in > v ddq ? 0.3v, f = 0 all speed grades 30 ma i sb3 automatic ce power-down current ? cmos inputs max. v dd , device deselected, or v in 0.3v or v in > v ddq ? 0.3v f = f max = 1/t cyc 6.0-ns cycle, 167 mhz 120 ma 6.7-ns cycle, 150 mhz 100 ma 7.5-ns cycle, 133 mhz 85 ma 10-ns cycle, 100 mhz 70 ma i sb4 automatic ce power-down current ? ttl inputs max. v dd , device deselected, v in v ih or v in v il , f = 0 all speed grades 70 ma shaded areas contain advance information. notes: 11. t a is the case temperature. 12. minimum voltage equals ? 2.0v for pulse durations of less than 20 ns. 13. the load used for v oh and v ol testing is shown in figure (b) of the a/c test conditions.
cy7c1370av25 cy7c1372av25 preliminary 20 capacitance [15] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = v ddq = 2.5v 4 pf c clk clock input capacitance 4 pf c i/o input/output capacitance 6.4 pf thermal resistance [15] description test conditions symbol tqfp typ. units thermal resistance (junction to ambient) still air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board q ja 25 c/w thermal resistance (junction to case) q jc 9 c/w notes: 14. input waveform should have a slew rate of > 1 v/ns. 15. tested initially and after any design or process change that may affect these parameters. output 5 ? r=1538 ? 5pf including jig and scope (a) (b) output r l =50 ? z 0 =50 ? v l = 1.25v 2.5v all input pulses [14] 2.5v gnd 90% 10% 90% 10% rise time: (c) ac test loads and waveforms 1 v/ns fall time: 1 v/ns
cy7c1370av25 cy7c1372av25 preliminary 21 switching characteristics over the operating range [16] -167 -150 -133 -100 parameter description min. max. min. max. min. max. min. max. unit clock t cyc clock cycle time 5.9 6.7 7.5 10.0 ns f max maximum operating frequency 167 150 133 100 mhz t ch clock high 2.4 2.6 3.0 3.5 ns t cl clock low 2.4 2.6 3.0 3.5 ns output times t co data output valid after clk rise 3.4 3.8 4.2 5.0 ns t eov oe low to output valid [15, 17, 19] 3.4 3.8 4.2 5.0 ns t doh data output hold after clk rise 1.5 1.5 1.5 1.5 ns t chz clock to high-z [15, 16, 17, 18, 19] 1.5 3.0 1.5 3.0 1.5 3.5 1.5 3.5 ns t clz clock to low-z [15, 16, 17, 18, 19] 1.5 1.5 1.5 1.5 ns t eohz oe high to output high-z [16, 17, 19] 3.0 3.0 3.5 3.5 ns t eolz oe low to output low-z [16, 17, 19] 0 0 0 0 ns set-up times t as address set-up before clk rise 1.5 1.5 1.5 1.5 ns t ds data input set-up before clk rise 1.5 1.5 1.5 1.5 ns t cens cen set-up before clk rise 1.5 1.5 1.5 1.5 ns t wes we , bws x set-up before clk rise 1.5 1.5 1.5 1.5 ns t als adv/ld set-up before clk rise 1.5 1.5 1.5 1.5 ns t ces chip select set-up 1.5 1.5 1.5 1.5 ns hold times t ah address hold after clk rise 0.5 0.5 0.5 0.5 ns t dh data input hold after clk rise 0.5 0.5 0.5 0.5 ns t cenh cen hold after clk rise 0.5 0.5 0.5 0.5 ns t weh we , bw x hold after clk rise 0.5 0.5 0.5 0.5 ns t alh adv/ld hold after clk rise 0.5 0.5 0.5 0.5 ns t ceh chip select hold after clk rise 0.5 0.5 0.5 0.5 ns shaded areas contain advance information. notes: 16. unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25v, i nput pulse levels of 0 to 2.5v, and output loading of the specified i ol /i oh and load capacitance. shown in (a), (b) and (c) of ac test loads. 17. t chz , t clz , t oev , t eolz , and t eohz are specified with ac test conditions shown in part (a) of ac test loads. transition is measured 200 mv from steady-state voltage. 18. at any given voltage and temperature, t eohz is less than t eolz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. device is designed to achieve high-z prior to low-z under the same system conditions. 19. this parameter is sampled and not 100% tested.
cy7c1370av25 cy7c1372av25 preliminary 22 switching waveforms cen clk address ce we & data in/out t cyc t ch t cl ra1 t ah t as t ws t wh t ces t ceh t co q4 q1 = don ? t care = undefined the combination of we & bws x (x = a, b, c, d for cy7c1370v25a & x = a, b for cy7c1372v25a) define a write cycle out d2 in d5 in out read write deselect write read read read suspend read deselect deselect wa2 ra3 ra4 wa5 ra6 ra7 t clz t doh q3 out t chz device originally deselected q7 out t chz t cens t cenh t doh bws x read/write/deselect sequence cen high blocks q6 out all synchronous inputs t ds t dh (see write cycle description table) ce is the combination of ce 1 , ce 2 , and ce 3 . all chip enables need to be active in order to select the device. any chip enable can deselect the device. rax stands for read address x, wax write address x, dx stands for data-in for location x, qx stands for data-out for location x. adv/ld held low. oe held low.
cy7c1370av25 cy7c1372av25 preliminary 23 switching waveforms (continued) adv/ld clk address ce data in/out t cyc t ch t cl t als t alh ra1 t ah t as t ces t ceh t co q1 = don ? t care = undefined the combination of we & bws x (x = a, b c, d) define a write cycle (see write cycle description table). out begin read burst read t clz t doh ce is the combination of ce 1 , ce 2 , and ce 3 . all chip enables need to be active in order to select the device. any chip enable can deselect the device. rax stands for read address x, wa stands for device originally deselected write address x, dx stands for data-in for location x, qx stands for data-out for location x. cen held wa2 q1+1 out q1+2 out q1+3 out ra3 t clz t chz d2+1 in d2+2 in d2+3 in d2 in t co q3 out t ds t dh burst read burst read begin write burst write burst write burst write begin read burst read burst read burst sequences bws x t ws t wh we t ws t wh low. during burst writes, byte writes can be conducted by asserting the appropriate bws x input signals. burst order determined by the state of the mode input. cen held low. oe held low.
cy7c1370av25 cy7c1372av25 preliminary 24 document #: 38-00989-a switching waveforms (continued) oe three-state i/os oe timing t eohz t eov t eolz ordering information speed (mhz) ordering code package name package type operating range 167 cy7c1370av25-167ac cy7c1372av25-167ac a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack commercial cy7c1370av25-167bgc CY7C1372AV25-167BGC bg119 119-ball bga (14 x 22 x 2.4 mm) 150 cy7c1370av25-150ac cy7c1372av25-150ac a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack cy7c1370av25-150bgc cy7c1372av25-150bgc bg119 119-ball bga (14 x 22 x 2.4 mm) 133 cy7c1370av25-133ac cy7c1372av25-133ac a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack cy7c1370av25-133bgc cy7c1372av25-133bgc bg119 119-ball bga (14 x 22 x 2.4 mm) 100 cy7c1370av25-100ac cy7c1372av25-100ac a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack cy7c1370av25-100bgc cy7c1372av25-100bgc bg119 119-ball bga (14 x 22 x 2.4 mm) shaded areas contain advance information.
cy7c1370av25 cy7c1372av25 preliminary 25 package diagram 100-pin thin plastic quad flatpack (14 x 20 x 1.4 mm) a101 $
cy7c1370av25 cy7c1372av25 preliminary ? cypress semiconductor corporation, 2000. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. revision history package diagram (continued) 119-lead fbga (14 x 22 x 2.4 mm) bg119 51-85115 document title: cy7c1370v25a/cy7c1372v25a document number: 38-00762 rev. ecn no. issue date orig. of change description of change ** 2997 4/11/00 mpr 1. new data sheet *a 3081 6/13/00 cxv 1. correct pin id, pins 43, b2

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